Senior ASIC RTL Engineer, Core IP

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide.

• Perform Verilog/SystemVerilog Register-Transfer Level (RTL) coding, functional/performance simulation debug and Lint/Cyber Defense Center (CDC)/VCLP checks.
• Participate in test planning and coverage analysis.
• Develop RTL implementations that meet engaged power, performance and area goals.
• Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up.
• Work with multi-disciplined and multi-site teams in Architecture, RTL design, verification, Design for Test (DFT) and Physical Design (PD).

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP), defining design constraints (SDC) and Low-power intent (UPF).

• 401k matching
• Health insurance
• Flight privileges

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